1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit, and more particularly is directed to a semiconductor integrated circuit with high withstanding voltage and stable and reliable characteristics.
2. Description of the Prior Art
There is proposed a semiconductor integrated circuit in which an isolation region of, for example, P-type conductivity is formed in a semiconductor base, a plurality of regions of N-type conductivity are divided in islands by the P-type isolation region, circuit elements are formed on each of the islands, respectively, and these islands are electrically isolated by PN-junctions formed between the islands and the isolation region. In this case, if an insulating layer made of, for example, silicon dioxide SiO.sub.2 is formed on the surface of the PN-junction for isolation extending to the surface of the substrate, an integrated circuit which may be high in withstanding voltage and in reliability can not be obtained. The integrated circuit of the prior art mentioned just above will be now described with reference to FIG. 1 in which two PNP-type transistors are formed on a common semiconductor substrate with their collectors being common. In the prior integrated circuit shown in FIG. 1, a semiconductor substrate 1 with high impurity concentration of P-type conductivity or low resistivity is prepared, a semiconductor layer 2 with relatively low impurity concentration of P-type conductivity is formed on the substrate 1 by an epitaxial method, and a semiconductor layer 3 with relatively low impurity concentration of N-type conductivity is also epitaxially formed on the layer 2 to form a semiconductor base 4. An insulating layer 5 made of, for example, silicon dioxide SiO.sub.2 is formed on an upper surface 4a of the semiconductor base 4 and a window 5c is then formed in the insulating layer 5 by photoetching. Through the window 5c, an impurity of P-type conductivity is selectively diffused into the semiconductor layer 3 to such an extent that the P-type impurity passes through the semiconductor layer 3 of N-type to form an isolation region 6 of P-type. Thus, the semiconductor layer 3 is divided into a plurality of regions by the isolation region 6 or two island regions 7a and 7b. In this case, upon the formation of the isolation region 6 by diffusion, an oxide layer or region insulating layer 5' is formed on the isolation regin 6 at the position of the window 5c to close the latter. A P-type impurity is selectively diffused into the respective island regions 7a and 7b to form P-type regions 8a and 8b. Thus, two PNP-type transistors 9a and 9b are formed respectively which have their common collector region made of the P-type substrate 1 and the semiconductor layer 2, their base regions made of the island regions 7a and 7b consisting of the N-type semiconductor 3 and isolated by the isolation region 6, and their emitter regions made of the P-type regions 8a and 8b.
With the integrated circuit described as above, the PN-junction J formed between the isolation region 6 and the island regions 7a and 7b electrically isolates the respective island regions 7a and 7b or the base regions of the transistors 9a and 9b, but it is ascertained that the withstanding voltage of the PN-junction J is relatively low and unstable. The low withstanding voltage and unstableness of the PN-junction J are caused by the fact that a positive surface level Q.sub.SS appears on the surface 4a of the base 4 due to the layer 5 of SiO.sub.2 and the surface portion of the isolation region 6 is partially reversed to the N-type by the positive surface level Q.sub.SS, as shown in FIG. 2, to form reverse regions 10 which extend from the islands or base regions 7a and 7b of the transistors 9a and 9b to the inside of the isolation region 6. In other words, the formation of the reverse regions 10 curves the PN-junction J near its surface portion to make its curvature large, so that its withstanding voltage is lowered by applying great electric field locally.
Further, since the isolation region 6 is formed by diffusion of the P-type impurity through the window 5c as described previously, the impurity concentration in the isolation region 6 near the surface 4a becomes high as it reaches the window 5c. Accordingly, PN-junctions J' formed by the reverse regions 10 near their end portions, which extend to the inside of the isolation region 6, are formed in the portion of the isolation region 6 in its high impurity concentration, so that the extension of the depletion layer in this portion is small when a reverse bias is applied to the PN-junction J', and hence the intensity of electric field applied thereto becomes great to lower its withstanding voltage.
Further, in the case where a wiring 11 made of conductive layer for electrically connecting the emitter of the transistor 9a with the base of the other transistor 9b is formed on the insulating layer 5 as shown in FIGS. 1 and 2, when a positive voltage is applied to the wiring 11, the formation of the reverse layer 10 is further increased by this positive voltage in addition to the surface level Q.sub.SS.
If the semiconductor pellet forming the integrated circuit is covered with resin mold to be protected, polarization is produced in the resin by some reasons to promote the formation of the reverse layer 10. By way of example, since the isolation region 6 is electricaly connected to the common collector region of the transistors 9a and 9b in the example of FIGS. 1 and 2, the characteristic relationship between a reverse bias voltage V.sub.CB across the collector-base of the transistors 9a and 9b and their collector-base current I.sub.CB is shown in FIG. 3 by a solid line which shows that the current I.sub.CB becomes large for relatively low reverse bias to the collector junction. Further, this characteristic is fluctuated up and down as indicated by arrows in FIG. 3. This fluctuation may be caused by, for example, changes of voltage applied to the wiring 11. In order to increase the withstanding voltage across the collector-base of the transistors and to obtain an ideal characteristic shown by a dotted line in FIG. 3, it is necessary to improve the withstanding voltage of the PN-junction and the stabilization or reliability of the isolation region 6.
In order to improve the withstanding voltage and reliability of the isolation region, such a construction shown in FIG. 4 is proposed in which a polycrystalline silicon layer 14 with high resistance, for example, with the resistivity of 2.5 .times. 10.sup.4 .OMEGA.cm is formed through the insulating layer 5 all over the surface 4a of the semiconductor base 4 in a range to which the PN-junction J formed by the isolation region 6 extends, and the polycrystalline layer 14 is made to be in ohmic contact at its both sides with the region 6 and the regions 7a and 7b over the junction J.
With this construction, the withstanding voltage can be made high as compared with that of the previously mentioned prior art one. That is, in an integrated circuit in which an isolation region is provided to achieve isolation by its PN-junction, since the PN-junction is always supplied with a reverse bias for the isolation, the polycrystalline silicon layer 14 of high resistance is supplied with voltage applied to the regions 6, 7a and 7b at the both sides of the silicon layer 14 gripping the PN-junction J, so that voltage gradient appears in the silicon layer 14 across the PN-junction. If a voltage of -100V (volts) is applied to the region 6 and a voltage of OV is applied to the regions 7a and 7b, by way of example, the voltage gradient of -100 to OV appears in the high resistance silicon layer 14. Accordingly, a negative voltage is applied to the junction J near its surface by the high resistance silicon layer 14 and hence the surface level Q.sub.SS is canceled to suppress the formation of the reverse layer. Further, the voltage gradient appeared in the high resistance silicon layer 14 acts to have a slow voltage gradient applied to the junction J extended to the surface 4a, so that the expansion of the depletion layer of the junction J can be slow in curvature to make gentle the concentration of electric field and hence to increase the withstanding voltage of the junction J as shown in FIG. 4 by a dotted line J.sub.d.
With the last prior art mentioned example, the withstanding voltage thereof can be increased as compared with that of the former example and the characteristic can be stabilized. However, in this second example, due to the voltage gradient produced in the silicon layer 14 of high resistance, a voltage of, for example, -80V indicated in FIG. 4 is applied to the surface portion of the junction J, and consequently a positive voltage of -80V - (-100)V = +20V is still applied to the same portion through the insulating layer 5, so that the withstanding voltage can not be improved sufficiently.